Low dropout linear regulator (LDO) has the characteristics of low power consumption, low noise, and small footprint on the chip, etc. LDO has been widely used in mobile electronic equipment.
Typical LDO architecture is shown in FIG. 1, comprising: an error amplifier EA, an adjustment transistor MP, a resistor divider feedback network comprising RF1 and RF2, a load current Iload, an output capacitor Cload (wherein RESR represents the output capacitor's equivalent series resistor). The basic working principle is: the resistance feedback network generates a feedback voltage through the resistor divider. The error amplifier amplifies the error between a reference voltage and the feedback voltage to control the gate voltage of the adjustment transistor. The adjustment transistor is used to adjust an output voltage. The whole network forms a negative feedback structure, so that the output voltage is stable. Due to the clamping effect of the error amplifier, the reference voltage VREF and the contact voltages VFB of RF1 and RF2 are equal. Thus, the following formula is satisfied:VOUT=VREF·(1+RF1/RF2).
The transient response of the LDO is the indicator of the LDO loop adjustment speed when transient changes of the load current Iload occur. The transient response of the LDO is limited by both the loop bandwidth limit and the output slew rate of the EA, while in the LDO, the output slew rate of the EA is typically determined by the EA output capacitor CPAR (i.e., the parasitic gate capacitance of the power transistor) and the large signal output current of the EA, that is the slew rate current ISR, satisfying the formula: SR=ISR/CPAR. When the load current Iload suddenly increases, the current of the adjustment transistor remains unchanged, so that the VOUT suddenly drops. The resistance feedback network feeds the change amount to the EA. Since the reference voltage is constant, the output voltage of the EA drops, so that the |VGS| of the adjustment transistor MP decreases. The current of MP decreases until it equals to the load current. The VOUT restores stability. Throughout the loop adjustment, the response speed of the EA is limited by its unity gain bandwidth. Since the gate of MP has a large parasitic capacitance CPAR, changing the gate voltage of MP needs a large EA output current ISR to charge and discharge the gate, namely, the slew rate limit. The selection of the size of MP needs to guarantee the passing of the maximum load current. Thus, the size is usually very large, resulting in a large parasitic gate capacitance. While introducing the ultra-low frequency poles and limiting the bandwidth of the EA, the slew rate of EA output is limited. In order to achieve high gain and low power consumption, a smaller bias current will be selected for the EA with the traditional structure, which will lead to a larger output impedance of the EA. The poles will be pushed towards the low frequency. The EA bandwidth will be limited. In addition, since the current of the output SR is insufficient, the output of the slew rate is limited. Therefore, the LDO transient response of the general structure is limited by the maximum load current, loop gain, and static power consumption.